1. Field of the Invention
The embodiments of the invention generally relate to complementary metal oxide semiconductor (CMOS) device fabrication, and more particularly to a method of forming dual self-aligned silicide in CMOS technologies to improve device performance.
2. Description of the Related Art
The term salicide, which stands for Self-ALIgned siliCIDE, refers to a silicide formed by a self-aligning method. A salicide is typically formed by depositing a metal layer (such as Ti, Co, Ni, etc.) over a silicon layer, and then annealing the semiconductor structure. Where the metal is in contact with the exposed silicon or polysilicon, a silicide is formed. Un-reacted metal is then selectively etched away, leaving the silicide automatically aligned to the underlying conductive gate (commonly polysilicon) and source/drain structure. The terms “silicide” and “salicide” are used interchangeably herein. Salicide processes are commonly implemented in MOS (metal oxide semiconductor) and CMOS processes to reduce contact resistance and sheet resistance.
FIG. 1 illustrates a conventional CMOS device 51 having the same silicide on each side (NFET (N-type field effect transistor) 80 and PFET (P-type field effect transistor) 70 side) of the device 51. The CMOS device 51 consists of a substrate 52 with Nwell (N-type retrograde well) and Pwell (P-type retrograde well) regions 53, 54, respectively configured therein. Shallow trench isolation regions 55 are also included in the CMOS device 51. The NFET portion 80 of the CMOS device 51 comprises a NFET gate 58 capped by a silicide layer 60. Additionally, insulative sidewall spacers 59 are configured around the NFET gate 58. A NFET gate dielectric 57 is positioned below the NFET gate 58. Moreover, NFET source/drain implant regions 68 comprising NFET source/drain silicide contacts 56 are also formed in the Pwell region 54 on opposite sides of the NFET gate 58. Likewise, the PFET portion 70 of the CMOS device 51 comprises a PFET gate 63 capped by a silicide layer 67. Additionally, insulative sidewall spacers 61 are configured around the PFET gate 63. A PFET gate dielectric 62 is positioned below the PFET gate 63. Additionally, PFET source/drain implant regions 69 comprising PFET source/drain silicide contacts 66 are also formed in the Nwell region 53 on opposite sides of the PFET gate 63. As indicated by the uniform hatching designation in FIG. 1, the NFET source/drain silicide 56, NFET gate silicide layer 60, PFET source/drain silicide 66, and PFET gate silicide layer 67 all comprise the same silicide material.
However, one of the drawbacks of this approach is non-optimal device performance when compared with a dual salicide approach. In fact, the performance of the NFET and PFET regions in a CMOS device could be optimized by applying different kinds of silicide (dual salicide process) in the respective NFET and PFET areas (for the source/drain and gate areas).
FIGS. 2 through 4 illustrate iterative steps of forming a conventional dual salicide CMOS device 1 (i.e., a CMOS device 1 formed of two different silicide materials). Generally, as illustrated in FIG. 2, the dual salicide process involves depositing a first silicide block film (such as oxide or nitride film) 14 over the entire device 1. Then, a first lithographic pattern and etching process is performed to remove a portion of the blocking film 14 over the NFET region 40 of the device 1. The NFET region 40 consists of a Pwell 4 formed in a substrate 2 with NFET source/drain implant regions 18 formed in the Pwell 4, a NFET gate dielectric 7 formed over the Pwell 4, and with a NFET gate 8 formed over the gate dielectric 7. A pair of insulative sidewalls 9 is also formed around the NFET gate 8. Additionally, shallow trench isolation regions 5 are also included in the CMOS device 1. The remaining portion of the film 14 protects the PFET region 30 of the device 1. The PFET region 30 is similarly configured to the NFET region 40, wherein the PFET region 30 consists of a Nwell 3 formed in the substrate 2 with PFET source/drain implant regions 19 formed in the Nwell 3, with a PFET gate dielectric 12 formed over the Nwell 3, and with a PFET gate 13 formed over the PFET gate dielectric 12. A pair of insulative sidewalls 11 is formed around the PFET gate 13 as well. A salicide process is performed over the NFET region 40 to form a silicide layer 10 over the NFET gate 8 as well as forming NFET source/drain silicide contacts 6.
Next, as shown in FIG. 3, the first blocking film 14 is removed from the device 1, and a second silicide blocking film (such as oxide or nitride film) 15 is deposited over the entire device 1. Then, a second lithographic pattern and etching process is performed to remove a portion of the blocking film 15 over the PFET region 30 of the device 1. Thereafter, a salicide process is performed over the PFET region 30 to form a silicide layer 17 over the PFET gate 13 as well as forming a PFET source/drain silicide contacts 16. As shown in FIG. 4, the silicide on the NFET portion 40 of the device 1 is different from the silicide on the PFET portion 30 of the device 1.
However, one of the problems with the conventional two lithography level dual salicide process as provided in FIGS. 2–4 is the misalignment caused during the processing between the two lithography levels as illustrated in FIG. 5 (the dotted circle represents the area of the device 1 where the misalignment occurs). This misalignment between the NFET region 40 and PFET region 30 results in an underlay in the device 1 (illustrated in FIG. 5 as a SRAM (synchronous random access memory) cell layout), which can cause high sheet resistance or an open circuit in the device and/or circuit areas thereby resulting in inferior device/circuit performance. Therefore, there remains a need for a novel dual salicide process, which overcomes this misalignment problem.